deep dive Not long after rejoining Intel in 2021, former CEO Pat Gelsinger announced an ambitious plan to reinvent the chipmaker as a contract semiconductor manufacturing powerhouse.
Four years later, Gelsinger has moved on, but his dream is still very much alive. Earlier this summer, Intel quietly began operating the first of two new leading-edge wafer fabs located at its Occotilo manufacturing plant in Chandler, Arizona.
Inside the belly of the beast
Last week, during Intel’s Tech Tour press event, El Reg had the opportunity to tour Fab52, where mass production of chips based on the company’s new 18A process node is already underway.
The facility, which broke ground in late 2021, comprises 600,000 cubic meters of concrete and 110,000 tons of steel. Access to the heart of the facility is tightly controlled and requires covering oneself head to toe in a cleanroom suit affectionately known as a bunny suit.
Access to Fab52’s inner workings requires donning a “bunny suit” designed to protect the wafers and equipment from contamination
The awkward getup, which thousands of Intel employees wear everyday, is essential to maintaining the fab’s hyper-sterile operating environment, which at any given moment has fewer than 10 particles per cubic foot of air. For reference, Intel tells us a hospital operating room may have in excess of 100,000 particles in the same space.
Entering through Fab42, which was built in 2011, the walls are bathed in a pale amber, which, much like a darkroom, is intended to minimize blue light that might interfere with the lithography process.
Overhead, claw-like carts zip about on rails carrying wafers and other equipment between the various buildings on the one million square-foot campus. Twenty-one hundred of these vehicles circle the 30 miles of track connecting the facilities, each traveling upwards of 90 miles a day.
Passing into Fab52, the light cools noticeably, as lithography has moved on and the equipment is no longer as sensitive as it once was. Here, the sheer scale and complexity of modern chipmaking becomes evident. At the heart of the facility are a series of ASML’s Extreme Ultra Violet (EUV) lithograph machines, the specific names of which we were asked not to disclose. With that said, the list is pretty easy to figure out, considering the Dutch equipment vendor is sole supplier of EUV machines.
At the heart of the Fab52 is ASMLs monolithic Extreme Ultra Violet lithography machines
The massive apparatus dwarfs anything found in the older Fab42: It’s roughly the length of a city bus and extends downward to the floor below. Inside, lasers vaporize droplets of molten tin forming a plasma which emits light in the EUV spectrum. Using a complex series of mirrors, features are imprinted on the photoresist-covered wafers.
This process is, of course, hidden from sight.
Gelsinger’s dream
The production at Fab52 represents the culmination of Gelsinger’s dream not only to expand Intel’s US manufacturing capacity but regain its technologic advantage, and with luck, establish itself as a leading edge foundry second only to TSMC. (If you’re curious about the name, Intel’s fab numbering went from 1 to 12, then increased by increments of 10 so the company didn’t have to have a “Fab 13” – much like many office buildings superstitiously lack a 13th floor.)
At the time it was announced, many had doubts that Intel could pull it off. The company’s 7nm manufacturing process was badly delayed and it’d only just managed to bring its 10nm process tech to market.
Just months earlier, Apple had released its first M-series silicon on TSMC’s 5nm process node. Even after rebranding its 10 and 7nm tech as Intel 7 and Intel 4 to better reflect its manufacturing capabilities, the gulf between the two foundries would only grow.
By 2024, Intel had outsourced most of its client computing lineup to rival TSMC. However, the tide is starting to reverse as Intel ramps production of the 18A process that’ll power its next generation of CPUs and System on Chips at Fab52 starting in 2026.
A return to process leadership
Teased not long after Intel announced its Arizona fab expansion, 18A is a 2nm class process node. The “A” here refers to angstroms of which there are 10 to a nanometer — though we should note that nothing on the chip is actually 18 angstroms in size.
At Intel’s Tech Tour in Arizona last week, the company touted the transistor tech as the most sophisticated semiconductor node in the world, and technically they’re not wrong.
18A is the chipmaker’s first process node to go to production using a gate-all-around (GAA) transistor design, which the foundry upstart has taken to calling RibbonFET.
Here’s a cross section of Intel’s gate-all-around transistor design
In this design, the transistor’s gate completely encircles the sources which reduces power leakage and transistor density. Intel claims that the new transistor design boosts performance per watt by 15 percent compared to the older Intel 3 process.
However, Intel isn’t the first to use GAA. Samsung employed the tech in its 3nm process node, though it wasn’t widely adopted, reportedly due to poor yields on the process.
TSMC is also bringing its own 2nm process tech to market next year, with AMD’s MI450-series accelerators being among the first to use it, but only Intel has managed to bring a new 2nm class part to market that also uses backside power.
Indeed, what really sets 18A apart is the use of backside power delivery, which Intel calls PowerVIA. Normally during the fabrication process, massive lithography machines etch transistors into silicon on top of which signal and power lines are routed. As transistor densities have increased, it has become increasingly difficult to route these lines efficiently.
By shifting power delivery to back side of the wafer, Intel is able to achieve higher transistor density
As you might have already guessed, with PowerVIA, Intel moved the power lines to the back of the wafer, freeing up space for more efficient signaling and, more importantly, better transistor density. If Intel is to be believed, the technology has allowed it to increase chip density by 30 percent.
TSMC isn’t slated to adopt backside power until the introduction of its A16 process tech late next year.
The first chips based on 18A, on the other hand, are set for release following CES in January, beginning with Intel’s Panther Lake client processors followed by its Clearwater Forest Xeons later in the year.
A sales pitch for Intel Foundry
If these products perform as Intel claims, and it can achieve acceptable yields, 18A could represent a sea change for the embattled chipmaker, which has struggled to convince customers to take the chance on its fledgling foundry business.
Compared to last gen’s Lunar Lake and Arrow Lake parts, which you may recall were based on TSMC’s 3nm process tech, Intel expects Panther Lake to deliver 10 percent higher single-threaded performance per watt. Meanwhile, Intel tells us that it expects Clearwater Forest to be approximately 17 percent faster than its Intel 3-based Sierra Forest 6900E series parts while consuming 10 percent less power.
These chips are not only critical to clawing back market share lost to AMD and Arm, but also represent a sales pitch for its foundry business, which in addition to leading-edge silicon also offers both 2.5D and 3D advanced packaging services.
- Taiwan gets chippy about US request it shifts manufacturing
- Trump’s tariff‑shaped stick can’t beat reality on US chip fabbing
- Intel’s open source future in question as exec says he’s done carrying the competition
- Panther Lake sets stage for Intel’s 2 nm comeback, but many details still TBD
Before his abrupt “retirement” last year, Gelsinger had hoped to bring on contract manufacturing customers with 18A, Intel now expects its upcoming 14A process tech to be Foundry’s first mainstream process node.
As we learned in April at Intel’s Foundry Direct Connect event, 14A is expected to deliver a 15-20 percent performance per watt uplift, but it isn’t expected to hit the market until 2027 at the earliest.
In the meantime, Intel is prepping two new variants of 18A called 18A-P and 18A-PT. The first is expected to deliver eight percent better performance per watt, while the second is designed optimized for chips requiring through silicon vias (TSVs), making it ideal as a base die for 3D-stacked packages.
It’s in Tan and Uncle Sam’s hands now
Of course all of this depends on Intel finding a foundry customer, something that now falls to CEO Lip Bu Tan, and here’s where things get a bit rocky.
This spring, Tan suggested that the future of Foundry would live or die on the success of 14A, and that if it couldn’t find a customer, the company may abandon its foundry ambitions.
However, that was before Uncle Sam carved out a 10 percent slice of Intel citing Foundry as a key national security asset. ®
deep dive Not long after rejoining Intel in 2021, former CEO Pat Gelsinger announced an ambitious plan to reinvent the chipmaker as a contract semiconductor manufacturing powerhouse.
Four years later, Gelsinger has moved on, but his dream is still very much alive. Earlier this summer, Intel quietly began operating the first of two new leading-edge wafer fabs located at its Occotilo manufacturing plant in Chandler, Arizona.
Inside the belly of the beast
Last week, during Intel’s Tech Tour press event, El Reg had the opportunity to tour Fab52, where mass production of chips based on the company’s new 18A process node is already underway.
The facility, which broke ground in late 2021, comprises 600,000 cubic meters of concrete and 110,000 tons of steel. Access to the heart of the facility is tightly controlled and requires covering oneself head to toe in a cleanroom suit affectionately known as a bunny suit.
Access to Fab52’s inner workings requires donning a “bunny suit” designed to protect the wafers and equipment from contamination
The awkward getup, which thousands of Intel employees wear everyday, is essential to maintaining the fab’s hyper-sterile operating environment, which at any given moment has fewer than 10 particles per cubic foot of air. For reference, Intel tells us a hospital operating room may have in excess of 100,000 particles in the same space.
Entering through Fab42, which was built in 2011, the walls are bathed in a pale amber, which, much like a darkroom, is intended to minimize blue light that might interfere with the lithography process.
Overhead, claw-like carts zip about on rails carrying wafers and other equipment between the various buildings on the one million square-foot campus. Twenty-one hundred of these vehicles circle the 30 miles of track connecting the facilities, each traveling upwards of 90 miles a day.
Passing into Fab52, the light cools noticeably, as lithography has moved on and the equipment is no longer as sensitive as it once was. Here, the sheer scale and complexity of modern chipmaking becomes evident. At the heart of the facility are a series of ASML’s Extreme Ultra Violet (EUV) lithograph machines, the specific names of which we were asked not to disclose. With that said, the list is pretty easy to figure out, considering the Dutch equipment vendor is sole supplier of EUV machines.
At the heart of the Fab52 is ASMLs monolithic Extreme Ultra Violet lithography machines
The massive apparatus dwarfs anything found in the older Fab42: It’s roughly the length of a city bus and extends downward to the floor below. Inside, lasers vaporize droplets of molten tin forming a plasma which emits light in the EUV spectrum. Using a complex series of mirrors, features are imprinted on the photoresist-covered wafers.
This process is, of course, hidden from sight.
Gelsinger’s dream
The production at Fab52 represents the culmination of Gelsinger’s dream not only to expand Intel’s US manufacturing capacity but regain its technologic advantage, and with luck, establish itself as a leading edge foundry second only to TSMC. (If you’re curious about the name, Intel’s fab numbering went from 1 to 12, then increased by increments of 10 so the company didn’t have to have a “Fab 13” – much like many office buildings superstitiously lack a 13th floor.)
At the time it was announced, many had doubts that Intel could pull it off. The company’s 7nm manufacturing process was badly delayed and it’d only just managed to bring its 10nm process tech to market.
Just months earlier, Apple had released its first M-series silicon on TSMC’s 5nm process node. Even after rebranding its 10 and 7nm tech as Intel 7 and Intel 4 to better reflect its manufacturing capabilities, the gulf between the two foundries would only grow.
By 2024, Intel had outsourced most of its client computing lineup to rival TSMC. However, the tide is starting to reverse as Intel ramps production of the 18A process that’ll power its next generation of CPUs and System on Chips at Fab52 starting in 2026.
A return to process leadership
Teased not long after Intel announced its Arizona fab expansion, 18A is a 2nm class process node. The “A” here refers to angstroms of which there are 10 to a nanometer — though we should note that nothing on the chip is actually 18 angstroms in size.
At Intel’s Tech Tour in Arizona last week, the company touted the transistor tech as the most sophisticated semiconductor node in the world, and technically they’re not wrong.
18A is the chipmaker’s first process node to go to production using a gate-all-around (GAA) transistor design, which the foundry upstart has taken to calling RibbonFET.
Here’s a cross section of Intel’s gate-all-around transistor design
In this design, the transistor’s gate completely encircles the sources which reduces power leakage and transistor density. Intel claims that the new transistor design boosts performance per watt by 15 percent compared to the older Intel 3 process.
However, Intel isn’t the first to use GAA. Samsung employed the tech in its 3nm process node, though it wasn’t widely adopted, reportedly due to poor yields on the process.
TSMC is also bringing its own 2nm process tech to market next year, with AMD’s MI450-series accelerators being among the first to use it, but only Intel has managed to bring a new 2nm class part to market that also uses backside power.
Indeed, what really sets 18A apart is the use of backside power delivery, which Intel calls PowerVIA. Normally during the fabrication process, massive lithography machines etch transistors into silicon on top of which signal and power lines are routed. As transistor densities have increased, it has become increasingly difficult to route these lines efficiently.
By shifting power delivery to back side of the wafer, Intel is able to achieve higher transistor density
As you might have already guessed, with PowerVIA, Intel moved the power lines to the back of the wafer, freeing up space for more efficient signaling and, more importantly, better transistor density. If Intel is to be believed, the technology has allowed it to increase chip density by 30 percent.
TSMC isn’t slated to adopt backside power until the introduction of its A16 process tech late next year.
The first chips based on 18A, on the other hand, are set for release following CES in January, beginning with Intel’s Panther Lake client processors followed by its Clearwater Forest Xeons later in the year.
A sales pitch for Intel Foundry
If these products perform as Intel claims, and it can achieve acceptable yields, 18A could represent a sea change for the embattled chipmaker, which has struggled to convince customers to take the chance on its fledgling foundry business.
Compared to last gen’s Lunar Lake and Arrow Lake parts, which you may recall were based on TSMC’s 3nm process tech, Intel expects Panther Lake to deliver 10 percent higher single-threaded performance per watt. Meanwhile, Intel tells us that it expects Clearwater Forest to be approximately 17 percent faster than its Intel 3-based Sierra Forest 6900E series parts while consuming 10 percent less power.
These chips are not only critical to clawing back market share lost to AMD and Arm, but also represent a sales pitch for its foundry business, which in addition to leading-edge silicon also offers both 2.5D and 3D advanced packaging services.
- Taiwan gets chippy about US request it shifts manufacturing
- Trump’s tariff‑shaped stick can’t beat reality on US chip fabbing
- Intel’s open source future in question as exec says he’s done carrying the competition
- Panther Lake sets stage for Intel’s 2 nm comeback, but many details still TBD
Before his abrupt “retirement” last year, Gelsinger had hoped to bring on contract manufacturing customers with 18A, Intel now expects its upcoming 14A process tech to be Foundry’s first mainstream process node.
As we learned in April at Intel’s Foundry Direct Connect event, 14A is expected to deliver a 15-20 percent performance per watt uplift, but it isn’t expected to hit the market until 2027 at the earliest.
In the meantime, Intel is prepping two new variants of 18A called 18A-P and 18A-PT. The first is expected to deliver eight percent better performance per watt, while the second is designed optimized for chips requiring through silicon vias (TSVs), making it ideal as a base die for 3D-stacked packages.
It’s in Tan and Uncle Sam’s hands now
Of course all of this depends on Intel finding a foundry customer, something that now falls to CEO Lip Bu Tan, and here’s where things get a bit rocky.
This spring, Tan suggested that the future of Foundry would live or die on the success of 14A, and that if it couldn’t find a customer, the company may abandon its foundry ambitions.
However, that was before Uncle Sam carved out a 10 percent slice of Intel citing Foundry as a key national security asset. ®
deep dive Not long after rejoining Intel in 2021, former CEO Pat Gelsinger announced an ambitious plan to reinvent the chipmaker as a contract semiconductor manufacturing powerhouse.
Four years later, Gelsinger has moved on, but his dream is still very much alive. Earlier this summer, Intel quietly began operating the first of two new leading-edge wafer fabs located at its Occotilo manufacturing plant in Chandler, Arizona.
Inside the belly of the beast
Last week, during Intel’s Tech Tour press event, El Reg had the opportunity to tour Fab52, where mass production of chips based on the company’s new 18A process node is already underway.
The facility, which broke ground in late 2021, comprises 600,000 cubic meters of concrete and 110,000 tons of steel. Access to the heart of the facility is tightly controlled and requires covering oneself head to toe in a cleanroom suit affectionately known as a bunny suit.
Access to Fab52’s inner workings requires donning a “bunny suit” designed to protect the wafers and equipment from contamination
The awkward getup, which thousands of Intel employees wear everyday, is essential to maintaining the fab’s hyper-sterile operating environment, which at any given moment has fewer than 10 particles per cubic foot of air. For reference, Intel tells us a hospital operating room may have in excess of 100,000 particles in the same space.
Entering through Fab42, which was built in 2011, the walls are bathed in a pale amber, which, much like a darkroom, is intended to minimize blue light that might interfere with the lithography process.
Overhead, claw-like carts zip about on rails carrying wafers and other equipment between the various buildings on the one million square-foot campus. Twenty-one hundred of these vehicles circle the 30 miles of track connecting the facilities, each traveling upwards of 90 miles a day.
Passing into Fab52, the light cools noticeably, as lithography has moved on and the equipment is no longer as sensitive as it once was. Here, the sheer scale and complexity of modern chipmaking becomes evident. At the heart of the facility are a series of ASML’s Extreme Ultra Violet (EUV) lithograph machines, the specific names of which we were asked not to disclose. With that said, the list is pretty easy to figure out, considering the Dutch equipment vendor is sole supplier of EUV machines.
At the heart of the Fab52 is ASMLs monolithic Extreme Ultra Violet lithography machines
The massive apparatus dwarfs anything found in the older Fab42: It’s roughly the length of a city bus and extends downward to the floor below. Inside, lasers vaporize droplets of molten tin forming a plasma which emits light in the EUV spectrum. Using a complex series of mirrors, features are imprinted on the photoresist-covered wafers.
This process is, of course, hidden from sight.
Gelsinger’s dream
The production at Fab52 represents the culmination of Gelsinger’s dream not only to expand Intel’s US manufacturing capacity but regain its technologic advantage, and with luck, establish itself as a leading edge foundry second only to TSMC. (If you’re curious about the name, Intel’s fab numbering went from 1 to 12, then increased by increments of 10 so the company didn’t have to have a “Fab 13” – much like many office buildings superstitiously lack a 13th floor.)
At the time it was announced, many had doubts that Intel could pull it off. The company’s 7nm manufacturing process was badly delayed and it’d only just managed to bring its 10nm process tech to market.
Just months earlier, Apple had released its first M-series silicon on TSMC’s 5nm process node. Even after rebranding its 10 and 7nm tech as Intel 7 and Intel 4 to better reflect its manufacturing capabilities, the gulf between the two foundries would only grow.
By 2024, Intel had outsourced most of its client computing lineup to rival TSMC. However, the tide is starting to reverse as Intel ramps production of the 18A process that’ll power its next generation of CPUs and System on Chips at Fab52 starting in 2026.
A return to process leadership
Teased not long after Intel announced its Arizona fab expansion, 18A is a 2nm class process node. The “A” here refers to angstroms of which there are 10 to a nanometer — though we should note that nothing on the chip is actually 18 angstroms in size.
At Intel’s Tech Tour in Arizona last week, the company touted the transistor tech as the most sophisticated semiconductor node in the world, and technically they’re not wrong.
18A is the chipmaker’s first process node to go to production using a gate-all-around (GAA) transistor design, which the foundry upstart has taken to calling RibbonFET.
Here’s a cross section of Intel’s gate-all-around transistor design
In this design, the transistor’s gate completely encircles the sources which reduces power leakage and transistor density. Intel claims that the new transistor design boosts performance per watt by 15 percent compared to the older Intel 3 process.
However, Intel isn’t the first to use GAA. Samsung employed the tech in its 3nm process node, though it wasn’t widely adopted, reportedly due to poor yields on the process.
TSMC is also bringing its own 2nm process tech to market next year, with AMD’s MI450-series accelerators being among the first to use it, but only Intel has managed to bring a new 2nm class part to market that also uses backside power.
Indeed, what really sets 18A apart is the use of backside power delivery, which Intel calls PowerVIA. Normally during the fabrication process, massive lithography machines etch transistors into silicon on top of which signal and power lines are routed. As transistor densities have increased, it has become increasingly difficult to route these lines efficiently.
By shifting power delivery to back side of the wafer, Intel is able to achieve higher transistor density
As you might have already guessed, with PowerVIA, Intel moved the power lines to the back of the wafer, freeing up space for more efficient signaling and, more importantly, better transistor density. If Intel is to be believed, the technology has allowed it to increase chip density by 30 percent.
TSMC isn’t slated to adopt backside power until the introduction of its A16 process tech late next year.
The first chips based on 18A, on the other hand, are set for release following CES in January, beginning with Intel’s Panther Lake client processors followed by its Clearwater Forest Xeons later in the year.
A sales pitch for Intel Foundry
If these products perform as Intel claims, and it can achieve acceptable yields, 18A could represent a sea change for the embattled chipmaker, which has struggled to convince customers to take the chance on its fledgling foundry business.
Compared to last gen’s Lunar Lake and Arrow Lake parts, which you may recall were based on TSMC’s 3nm process tech, Intel expects Panther Lake to deliver 10 percent higher single-threaded performance per watt. Meanwhile, Intel tells us that it expects Clearwater Forest to be approximately 17 percent faster than its Intel 3-based Sierra Forest 6900E series parts while consuming 10 percent less power.
These chips are not only critical to clawing back market share lost to AMD and Arm, but also represent a sales pitch for its foundry business, which in addition to leading-edge silicon also offers both 2.5D and 3D advanced packaging services.
- Taiwan gets chippy about US request it shifts manufacturing
- Trump’s tariff‑shaped stick can’t beat reality on US chip fabbing
- Intel’s open source future in question as exec says he’s done carrying the competition
- Panther Lake sets stage for Intel’s 2 nm comeback, but many details still TBD
Before his abrupt “retirement” last year, Gelsinger had hoped to bring on contract manufacturing customers with 18A, Intel now expects its upcoming 14A process tech to be Foundry’s first mainstream process node.
As we learned in April at Intel’s Foundry Direct Connect event, 14A is expected to deliver a 15-20 percent performance per watt uplift, but it isn’t expected to hit the market until 2027 at the earliest.
In the meantime, Intel is prepping two new variants of 18A called 18A-P and 18A-PT. The first is expected to deliver eight percent better performance per watt, while the second is designed optimized for chips requiring through silicon vias (TSVs), making it ideal as a base die for 3D-stacked packages.
It’s in Tan and Uncle Sam’s hands now
Of course all of this depends on Intel finding a foundry customer, something that now falls to CEO Lip Bu Tan, and here’s where things get a bit rocky.
This spring, Tan suggested that the future of Foundry would live or die on the success of 14A, and that if it couldn’t find a customer, the company may abandon its foundry ambitions.
However, that was before Uncle Sam carved out a 10 percent slice of Intel citing Foundry as a key national security asset. ®
deep dive Not long after rejoining Intel in 2021, former CEO Pat Gelsinger announced an ambitious plan to reinvent the chipmaker as a contract semiconductor manufacturing powerhouse.
Four years later, Gelsinger has moved on, but his dream is still very much alive. Earlier this summer, Intel quietly began operating the first of two new leading-edge wafer fabs located at its Occotilo manufacturing plant in Chandler, Arizona.
Inside the belly of the beast
Last week, during Intel’s Tech Tour press event, El Reg had the opportunity to tour Fab52, where mass production of chips based on the company’s new 18A process node is already underway.
The facility, which broke ground in late 2021, comprises 600,000 cubic meters of concrete and 110,000 tons of steel. Access to the heart of the facility is tightly controlled and requires covering oneself head to toe in a cleanroom suit affectionately known as a bunny suit.
Access to Fab52’s inner workings requires donning a “bunny suit” designed to protect the wafers and equipment from contamination
The awkward getup, which thousands of Intel employees wear everyday, is essential to maintaining the fab’s hyper-sterile operating environment, which at any given moment has fewer than 10 particles per cubic foot of air. For reference, Intel tells us a hospital operating room may have in excess of 100,000 particles in the same space.
Entering through Fab42, which was built in 2011, the walls are bathed in a pale amber, which, much like a darkroom, is intended to minimize blue light that might interfere with the lithography process.
Overhead, claw-like carts zip about on rails carrying wafers and other equipment between the various buildings on the one million square-foot campus. Twenty-one hundred of these vehicles circle the 30 miles of track connecting the facilities, each traveling upwards of 90 miles a day.
Passing into Fab52, the light cools noticeably, as lithography has moved on and the equipment is no longer as sensitive as it once was. Here, the sheer scale and complexity of modern chipmaking becomes evident. At the heart of the facility are a series of ASML’s Extreme Ultra Violet (EUV) lithograph machines, the specific names of which we were asked not to disclose. With that said, the list is pretty easy to figure out, considering the Dutch equipment vendor is sole supplier of EUV machines.
At the heart of the Fab52 is ASMLs monolithic Extreme Ultra Violet lithography machines
The massive apparatus dwarfs anything found in the older Fab42: It’s roughly the length of a city bus and extends downward to the floor below. Inside, lasers vaporize droplets of molten tin forming a plasma which emits light in the EUV spectrum. Using a complex series of mirrors, features are imprinted on the photoresist-covered wafers.
This process is, of course, hidden from sight.
Gelsinger’s dream
The production at Fab52 represents the culmination of Gelsinger’s dream not only to expand Intel’s US manufacturing capacity but regain its technologic advantage, and with luck, establish itself as a leading edge foundry second only to TSMC. (If you’re curious about the name, Intel’s fab numbering went from 1 to 12, then increased by increments of 10 so the company didn’t have to have a “Fab 13” – much like many office buildings superstitiously lack a 13th floor.)
At the time it was announced, many had doubts that Intel could pull it off. The company’s 7nm manufacturing process was badly delayed and it’d only just managed to bring its 10nm process tech to market.
Just months earlier, Apple had released its first M-series silicon on TSMC’s 5nm process node. Even after rebranding its 10 and 7nm tech as Intel 7 and Intel 4 to better reflect its manufacturing capabilities, the gulf between the two foundries would only grow.
By 2024, Intel had outsourced most of its client computing lineup to rival TSMC. However, the tide is starting to reverse as Intel ramps production of the 18A process that’ll power its next generation of CPUs and System on Chips at Fab52 starting in 2026.
A return to process leadership
Teased not long after Intel announced its Arizona fab expansion, 18A is a 2nm class process node. The “A” here refers to angstroms of which there are 10 to a nanometer — though we should note that nothing on the chip is actually 18 angstroms in size.
At Intel’s Tech Tour in Arizona last week, the company touted the transistor tech as the most sophisticated semiconductor node in the world, and technically they’re not wrong.
18A is the chipmaker’s first process node to go to production using a gate-all-around (GAA) transistor design, which the foundry upstart has taken to calling RibbonFET.
Here’s a cross section of Intel’s gate-all-around transistor design
In this design, the transistor’s gate completely encircles the sources which reduces power leakage and transistor density. Intel claims that the new transistor design boosts performance per watt by 15 percent compared to the older Intel 3 process.
However, Intel isn’t the first to use GAA. Samsung employed the tech in its 3nm process node, though it wasn’t widely adopted, reportedly due to poor yields on the process.
TSMC is also bringing its own 2nm process tech to market next year, with AMD’s MI450-series accelerators being among the first to use it, but only Intel has managed to bring a new 2nm class part to market that also uses backside power.
Indeed, what really sets 18A apart is the use of backside power delivery, which Intel calls PowerVIA. Normally during the fabrication process, massive lithography machines etch transistors into silicon on top of which signal and power lines are routed. As transistor densities have increased, it has become increasingly difficult to route these lines efficiently.
By shifting power delivery to back side of the wafer, Intel is able to achieve higher transistor density
As you might have already guessed, with PowerVIA, Intel moved the power lines to the back of the wafer, freeing up space for more efficient signaling and, more importantly, better transistor density. If Intel is to be believed, the technology has allowed it to increase chip density by 30 percent.
TSMC isn’t slated to adopt backside power until the introduction of its A16 process tech late next year.
The first chips based on 18A, on the other hand, are set for release following CES in January, beginning with Intel’s Panther Lake client processors followed by its Clearwater Forest Xeons later in the year.
A sales pitch for Intel Foundry
If these products perform as Intel claims, and it can achieve acceptable yields, 18A could represent a sea change for the embattled chipmaker, which has struggled to convince customers to take the chance on its fledgling foundry business.
Compared to last gen’s Lunar Lake and Arrow Lake parts, which you may recall were based on TSMC’s 3nm process tech, Intel expects Panther Lake to deliver 10 percent higher single-threaded performance per watt. Meanwhile, Intel tells us that it expects Clearwater Forest to be approximately 17 percent faster than its Intel 3-based Sierra Forest 6900E series parts while consuming 10 percent less power.
These chips are not only critical to clawing back market share lost to AMD and Arm, but also represent a sales pitch for its foundry business, which in addition to leading-edge silicon also offers both 2.5D and 3D advanced packaging services.
- Taiwan gets chippy about US request it shifts manufacturing
- Trump’s tariff‑shaped stick can’t beat reality on US chip fabbing
- Intel’s open source future in question as exec says he’s done carrying the competition
- Panther Lake sets stage for Intel’s 2 nm comeback, but many details still TBD
Before his abrupt “retirement” last year, Gelsinger had hoped to bring on contract manufacturing customers with 18A, Intel now expects its upcoming 14A process tech to be Foundry’s first mainstream process node.
As we learned in April at Intel’s Foundry Direct Connect event, 14A is expected to deliver a 15-20 percent performance per watt uplift, but it isn’t expected to hit the market until 2027 at the earliest.
In the meantime, Intel is prepping two new variants of 18A called 18A-P and 18A-PT. The first is expected to deliver eight percent better performance per watt, while the second is designed optimized for chips requiring through silicon vias (TSVs), making it ideal as a base die for 3D-stacked packages.
It’s in Tan and Uncle Sam’s hands now
Of course all of this depends on Intel finding a foundry customer, something that now falls to CEO Lip Bu Tan, and here’s where things get a bit rocky.
This spring, Tan suggested that the future of Foundry would live or die on the success of 14A, and that if it couldn’t find a customer, the company may abandon its foundry ambitions.
However, that was before Uncle Sam carved out a 10 percent slice of Intel citing Foundry as a key national security asset. ®
