Analysis Arm executives this week tried to play down the threat of RISC-V to the silicon architect’s business.
Speaking to reporters at a press event, Dermot O’Driscoll, VP of product solutions at Arm, acknowledged that RISC-V was driving “some competition” against the British chip designer. “It’s a very exciting market right now,” he said. “It helps us all focus and make sure we’re doing better.”
O’Driscoll proceeded to highlight the strength of Arm’s intellectual property, licensing, customer relations, and software ecosystem, presumably in an attempt to draw attention to RISC-V’s comparative immaturity in these areas. While the RISC-V has been around since 2010, the free and open instruction set architecture (ISA) has only recently made its way into commercial products, he pointed out.
Despite this, the RISC-V world has captured considerable mindshare and hundreds of millions of dollars in funding in over the past few years, propelled in part by high-profile contracts. The architecture has proven good enough for NASA, which plans to use Microchip-designed processors with SiFive RISC-V CPU cores in its next-gen High-Performance Spaceflight Computer.
Just this week, SiFive, one of the leading RISC-V chipmakers, announced a full portfolio of chip designs aimed at automobile manufacturers.
“The RISC-V ecosystem is growing rapidly, and RISC-V companies like SiFive are rapidly hiring,” David Miller, head of corporate communications at SiFive, told The Register.
“Customers in automotive and aerospace are turning to the ecosystem – which is now widely taught in universities around the world — with confidence it will be strong and vibrant 10-15 years or more in the future.”
Additionally, semiconductor industry watcher Dylan Patel claimed this week Apple is shifting the non-application Arm cores in its mobile system-on-chip family to RISC-V counterparts.
As a reminder, the RISC-V ISA is openly available, and royalty free, as a specification; chip designers are expected to implement the standard themselves in their own CPU cores. If you stick to the spec, your processor will be able to run the same software as another processor following the same spec.
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While RISC-V may be gaining traction in some markets, Arm isn’t seemingly worried about the upstart ISA eroding its newfound foothold in the datacenter. Arm’s designs now power everything from servers to accelerators in all major public clouds.
“We really don’t see RISC-V as a significant competitor to us in the datacenter space right now, or in the near future,” Chris Bergey, SVP and GM of Arm’s Infrastructure business, said, characterizing the rival ISA as being better suited to niche or specialized applications.
“We do respect the community, but I think that if you look at these solutions that are being provided they’re quite unique,” he said of RISC-V.
Run the RISC
According to Bergey, RISC-V does work well as a starting point on which a large amount of customization can be done. The base RISC-V CPU ISA is relatively light and simple, with fewer than 50 instructions, and can be extended as needed by implementers to suit their applications.
There is a set of officially approved extensions to the ISA that can be selected and implemented in a RISC-V CPU core, or designers can come up with their own. These extensions include support for floating point math, atomic instructions, vector math, and so on.
There are benefits to keeping the ISA modular in this way, including the fact that chip engineers aren’t forced to include sets of instructions they don’t want or need, thereby reducing complexity at the risk of potentially losing some software compatibility. If you leave out an extension used by applications, those instructions will either need to be emulated in software or the apps can’t run.
Implementing ratified extensions is preferred, and if you do make your own, you’re encouraged to help turn it into a standard, so as to minimize fragmentation.
For its machine-learning-optimized X280 cores, SiFive opted to develop its own vector math extension and accompanying engine, which it says is 6X faster than what would be possible with the standard RISC-V vector extension.
Arm’d to the hilt
While Arm also offers architectural licenses for customers that want to develop custom cores from scratch that are compatible with the Arm ISA, more often than not chip companies end up using Arm’s off-the-shelf cores and chip IP, such as those in its Cortex and Neoverse lines.
Bergey’s argument appears to boil down to this: if you’re willing to go to the effort of developing your own CPU cores, RISC-V might be a good fit if you’re unwilling to fork out for and abide by an Arm architectural license.
But if you’re not willing to design your own CPU core, we’re told, Arm and its partners have plenty of designs to fit your specific use case that you can pick up, license, and drop into a system-on-chip.
Arm’s IP portfolio is extensive and well battle tested, though the RISC-V world does offer cores to license, too – for example, SiFive sells them – and free open source ones are available. In fact, several chip houses now offer fully fleshed-out core designs that are RISC-V compatible, which customers can license for use in their chips.
While Arm might not see RISC-V as a threat today, O’Driscoll said the company “absolutely will be keeping an eye on what RISC-V are doing” moving forward.
No doubt it is, as we note that Arm has made changes to the way it licenses cores in the wake of RISC-V’s growth. Faced with a royalty free, open, and modular rival, Arm has for instance taken steps to, in certain circumstances, reduce the upfront costs of licensing its IP and allowed licensees to add custom instructions.
RISC-V International, the ISA’s governing body, declined to comment. ®
